Altium

Design Rule Verification Report

Date:		8/31/2025
Time:		9:47:16 PM
Elapsed Time:		00:00:00
Filename:		C:\Users\Travis.James\Desktop\GA PDL Breakout Board_local\PDL_Gen4_Breakout\PDL_Gen4_Breakout\PDL_Gen4_Breakout\PDL_Gen4_Breakout.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=6mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=6mil) (Max=400mil) (Preferred=8mil) (All)	0
Routing Topology Rule(Topology=Shortest) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=16mil) (Conductor Width=6mil) (Air Gap=6mil) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=6mil) (All)	0
Hole Size Constraint (Min=13mil) (Max=265mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=3mil) (IsPad),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Board Clearance Constraint (Gap=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0